5. PASSIVE COMPONENTS FOR FULLY INTEGRATED ANALOG AND RF CIRCUITS
Several passive components are required to fully integrate analog and RF circuits in mixed-signal SOC ICs. These included analog resistors and capacitors, inductors, and varactors. This section describes how these elements can be realized in the aforementioned BiCMOS process.
In the process technology presented in this article, two high-density linear capacitors are available. Each requires one additional mask level to implement. The metal-oxide-metal (MOM) capacitor is designed for applications that require excellent linearity with a very low voltage coefficient (less than 40 ppm/V), and features a density of 1.0 fF/µm2. The MOM capacitor is formed by deposition of a 35-nm oxide layer between the layers of a standard Ti/TiN/AI metal stack. The multiple metal layers of standard CMOS are required to reduce, metal migration under an applied field. This capacitor requires the process step of oxide deposition, a photolithographic step to define the capacitors, an oxide etch, and a photo strip. The processed adds no thermal cycles. The matching of a metal-metal capacitor to an adjacent capacitor depends on the accuracy of the etching of the capacitor. In a modern deep-submicron CMOS process, etching must be very well controlled since metal-to-metal spacing is 0.2 µm or less. Assuming careful layout, the MOM capacitor can match to better than 0.1% level as a result of this careful etch control. This allows the development of data converters of 10 b or more without calibration or trimming.
Since the capacitor is made from metal, its series resistance is reduced. In turn, the capacitor’s effective Q is raised. The capacitor can be placed high up in a multiple metal stack, allowing significant reduction of the parasitic capacitance to substrate when compared to poly-poly capacitor.
For applications that require higher density, such as bypass capacitors, a linear MOS capacitor is available with a voltage coefficient of 0.4%/V and density of 6.0 fF/µm2. The linear MOS capacitor used the 5.0-nm gate oxide from the 3.3-V CMOS process with an additional arsenic implant to improve linearity.
5.1 RESISTORS
Several resistors are available in BiCMOS process technology and are summarized in Table 2.
TABLE2 RESISTOR PARAMETERS
Gate poly, n+ and p+ source/drain, and n-tub resistors are characterized from the digital CMOS process. The center value of these resistors may vary as adjustments are made in the core CMOS transistor for optimal performance and yield. The diffusion resistors have high parasitic capacitance, significant temperature coefficients, and linearity limitations. The most heavily used of these resistors is the n-tub, which has the highest resistively used in circuits. It is also extensively used in circuits designed to be functional in the digital CMOS process. The poly gate has a lower resistively as a result of the silicide process technology used in its formation. This results in a less dense resistor with potential significant variation. This is, however, the only linear resistor available in a standard digital process, unless special poly-resistor is available that has been designed a part of the ESD structure.
Emitter and base-poly resistors are available from the SiGe bipolar module. As with the diffusion resistors discussed above, the doping level of the emitter, and sometimes base poly, needs to be changed to optimize transistor performance and yield. This affects the nominal sheet resistance of the resistors. The precision base-poly resistor uses one additional mask to allow the sheet resistance to be tailored to a predetermined specification without disturbing the NPN transistor parameters. P-type base-poly resistors with targeted sheet resistance of 300 Ώ/sq have demonstrated excellent performance for RF analog applications. The sheet resistance values varied within +or-3.9% across the wafer and the temperature co-efficient of the resistor is 300 ppm with good voltage linearity.
5.2 CAPACITORS
Without any modules, a CMOS process offers only the gate-semiconductor capacitance for capacitor formation. Not only is this highly nonlinear as the device transition from accumulation to depletion, but it also results in a parasitic junction capacitance on silicon side of the device that makes the capacitor incompatible for many circuits. Traditional CMOS processes designed for analog-and mixed-signal applications have included an extra layer of polysilicon to form a poly-poly capacitor. This capacitor is much more linear and its parasitic capacitance from the lower poly layer to the substrate is significantly reduced. The introduction of the capacitor in the middle of the CMOS device processing cycle, however, is a drawback because the thermal process affects all the implants that precede it. More vertical topography that will affect the achievement of planarity in the latter stages of the process is also required as metal layers are added. From the perspective of the RF designer, the high series resistance of a poly-poly capacitor is a major disadvantage, given its low Q value.
In the BiCMOS process technology, two high-density linear capacitors are available. Each requires one additional mask level to implement. The metal-oxide-metal (MOM) capacitor is designed for applications that require excellent linearity with a very low voltage coefficient (less than 40 ppm/V), and features a density of 1.0 fF/um2 . The MOM capacitor is formed by deposition of a 35-nm oxide layer between the layers of a standard Ti/TiN/AI metal stack. The multiple metal layers of standard CMOS are required to reduce, metal migration under an applied field. This capacitor requires the process step of oxide deposition, a photolithographic step to define the capacitors, an oxide etch, and a photo strip. The processed adds no thermal cycles. The matching of a metal-metal capacitor to an adjacent capacitor depends on the accuracy of the etching of the capacitor. In a modern deep-submicron CMOS process, etching must be very well controlled since metal-to-metal spacing is 0.2 µm or less.
Since the capacitor is made from metal, its series resistance is reduced. In turn, the capacitor’s effective Q is raised. The capacitor can be placed high up in a multiple metal stack, allowing significant reduction of the parasitic capacitance to substrate when compared to poly-poly capacitor.
5.3 INDUCTORS
Conflicting substrate requirements limit the integration of high-Q inductors with high-performance CMOS devices. Inductors fabricated using CMOS technologies based on epi/p+ substrates [Figure 8a) are severely degraded because of eddy-current losses in the substrate, and typically maximum quality-factor Q reported on epi/p+ substrates is only 3. The p+ layer has a receptivity of roughly 0.01µ-cm and plays an important role in latch-up suppression and impurity gettering (attracting heavy metals away from the silicon surface) in CMOS devices.
FIGURE 8
Substrate option for integrated inductors a) conventional epi/p+ substrate for latch up resistant CMOS technology has only low Qb inductors b)conventional P- bulk substrate for high Q inductors c) modified substrate for high Q inductors and latch up resistant CMOS
The simple solution of changing to bulk substrate [Figure 8(b) enables the fabrication of high-Q inductors but may exact a price in refused device density (to prevent device latch up) and possible yield loss. Also, many of the reuse advantages in SOC integration would be voided. We next examine a modified substrate structure that addresses the conflicting goals of high Q and high from an established CMOS technology using epi/p+ substrates. Figure 8(c) shows the modified substrate structure that incorporates a blanket p+ BL positioned between a p- starting material and a p- epitaxial layer. The eddy current losses are limited to the thickness of the BL rather than the whole substrate, resulting in much higher inductor Q.
Silicon-on-insulator (SOI) is a recent advancement in process technology that can improve inductor Q. A 30% improvement in the quality factor of thick-aluminum inductors was measured, due to the absence of the p+ latch-up suppression layer.
5.4 VARACTORS
There are several options for implementing high-performance varactors. These can be categorized under two general headings: MOS and junction varactors. MOS varactors have been implemented using a no inverting PMOS structure that can be realized by removing p+ source/drain implants form a PMOS transistor and replacing them with N implants. Several different types of junction varactors are feasible using some of the available options as viable possibilities. These are base-emitter, base-collector, and p-nub junctions.
Varactors have three important performance parameters: Q Cmax/Cmin (maximum to minimum capacitance range over voltage), and tuning range (useful range over which the capacitance varies with voltage).
MOS varactors provide the best Cmax/Cmin (values as high as five have been achieved with the SiGe BiCMOS process). Base-emitter varactors have lower values (~2) while base-collector and p+-ntub varactors have similar but lower Cmax/Cmin (<1.5).>
An application of the technology so far described is introduced by Agere systems, Orlando, Florida for a 10 GB/s 16:1 multiplexer and 10 GHz clock synthesizer. The chip integrates 4,000 bipolar and 3,100 MOS devices on a 5.5 X 5.5-mm die and is packaged in a 225-pin ceramic ball grid array. The 10-GHz oscillator core used MOM capacitors, pMOS varactors, base resistors, and a chip inductor with a Q of 16 at 10 GHz.
To extend this BiCMOS process in to next generation, Texas instruments is tapping the benefit of complementary SiGe bipolar transistor. TI has developed a third generation of fully isolated complimentary SiGe BiCMOS for ultra high speed precision analog and mixed signal IC s. this process is expected to go into volume manufacturing by the end of this year.
7. CONCLUSION
Presented an overview of a SiGe modular BiCMOS process technology. Through the use of add-on modules compatible with the core CMOS process technology, large-scale chips combining digital, analog, and RF technologies can be produced. Modules are added as required by the chip under development. By using the core process with added modules, the economies of scale associated with large-volume CMOS production are maintained without compromising the performance of the analog or RF circuits. By enabling higher-speed devices and increased device density levels, these exciting advances in process technology will decrease the number of ICs and discrete (passive) components required by complex optical, wired and wireless communication systems. As process technology advances, we will see SOC systems with millions of digital gates combined with RF circuits operating in the tens of GHz. This will be made possible through enhanced photolithographic scaling and, potentially, SOI technology that could result in faster devices and better isolation between circuit blocks. The ability to easily connect to the bodies of the MOS device remains a problem for SOI technology when the MOS devices are used in analog or RF circuits. Perhaps of greater significance will be the development of novel device structures and process technology innovations as catalysts for next-generation SOC systems.
--------------------------------------------------------------------------------
Back to Electronics Topics
.jpg)
(8)
No comments:
Post a Comment