Along with active elements, modern RF and analog-circuit designs require high-quality passive components, including resistors, capacitors, inductors, and varactors. As with the bipolar device, it is essential that these components integrate into the core CMOS process with a minimum of cost adders or extension of the time to process introduction.
In this section, we look at a CMOS-based Bi-CMOS process technology that incorporates high-performance SiGe bipolar transistors, high-Q inductors, capacitors, Varactors, and precision resistors as modules to a core 0.14-µm CMOS process technology and is, thus, compatible with the requirements of mixed-signal SOC integrated circuits. While the information to follow is specific to the process developed at Agere Systems for production on 8-in wafers at the company’s Orlando, Florida, fab, many of the techniques described are also finding their way into process technology from other manufactures.
4.1 Technology Description of the Standard Deep-Submicron CMOS Process
4.1.1 Digital CMOS Core Process
The core 0.14-µm CMOS process; upon which the bipolar and passive modules will be added, uses p-epi/p substrate, shallow oxide trench isolation (STI), dual-gate oxides to support high-and low-breakdown voltage devices and dual-doped (P+ for PMOS devices and n+ for NMOS devices) tungsten polycide (WSI)- to reduce gate resistance-gates. The dual-doped gates ensure that both the PMOS and NMOS devices operate in the surface, not buried, channel mode of operation to reduce leakage. This allows for low NMOS and PMOS thresholds that facilitate operation below 1.5 V. The process also offers up to seven aluminum metal levels with tungsten plug vias (contacts) and inter-level dielectric with dielectric constants lower than traditional silicon dioxide. The high-performance 1.5-V NMOS and PMOS transistors feature 0.135-µm minimum gate length and 2.4-nm gate oxide, resulting in a ring oscillator delay of 22 ps/stage Low-power NMOS/PMOS transistors are also available in the CMOS process with low off current of 10 pA/µm. The vast majority of CMOS devices on the chip will use these devices to reduce power consumption when the gates are not active. Increasing the threshold voltages and slightly increasing channel length reduces leakage.
In addition, 3.3-V NMOS/PMOS transistor with aggressive 5.0-nm gate oxide and high-drive currents of 700/400-µA/µm are needed in the analog and RF portions of the circuits where a 1.5-V supply is not adequate for dynamic range requirements. Low supply voltages limit the number of devices that can be stacked, complicating the design of mixers and other circuit types. The vast majority of the digital gates must operate with the lower 1.5 V to reduce digital noise injected into the substrate. Noise injected in the substrate is a major problem when designing a mixed-digital/analog and RF systems, since this noise can degrade circuit performance.
4.1.2 Dense SRAM
4.1.3 PROCESS INTEGRATION OF THE SiGe DEVICE
FIGURE1 SiGe BiCMOS Schematic cross sectionThe NPN transistor module requires just four additional mask levels, using high-energy phosphorous implantation for the sub-collector and selective epitaxy for the SiGe base. The SiGe bipolar module does not alter the 0.14-µm digital CMOS device parameters. Standard shallow trench isolation is used to isolate bipolar transistors.
FIGURE 2 CMOS SiGe modular BiCMOS process flow
Figure 2 illustrates the BiCMOS process flow with key integration process steps. The starting material has a specially formed P+ blanket layer (BL) on a 10 Ώcm substrate to provide on-chip high-Q inductors while maintaining modularity and preserving the density and latch-up immunity needed for CMOS libraries. This starting material replaces the P-/p+ substrate of the standard CMOS devices targeted for 1.5-V and 3.3-V applications. The gate oxide is then formed, and the polysilicon gate deposited and etched. After forming the lightly doped drain (LDD) regions for the NMOS and PMOS devices, the process deviates from the CMOS flow with the SiGe bipolar process module dropped in (Figure 1).
In the SiGe process module, a high-energy implantation (HEI) is used to form the epi-free buried collector layer. Most high-performance bipolar processes use an expensive (in terms of added equipment/processing costs and potential yield loss) epitaxial BL to reduce the extrinsic collector resistance. The BL also introduces significant deviation from the core CMOS process. An alternative is high-energy ion implantation to replace the BL. This implantation step challenges process technologists because it is a deep, high-dose implant. Control of implant and preventing silicon surface damage are keys to successful HEI.
A thick photo-resist layer covers the CMOS area on the wafer during HEL to prevent contamination by the implant. The photo-resist layer is specially treated by extended thermal baking and UV hardening before HEI to prevent resist cracking and peeling during HEI. An insulating oxide layer is deposited after HEI, then, a layer of amorphous polysilicon is deposited. The polysilicon layer will form the extrinsic base contact for the bipolar device. The transistor’s extrinsic base is heavily doped with p+ boron to reduce base resistance. A thick nitride layer on top of the amorphous silicon base provides isolation between the base polysilicon and the emitter polysilicon that will be deposited later. After cutting the emitter window through the nitride and amorphous silicon stack, an optional selective collector implant (SIC) is introduced (Figure 3)
FIGURE 3 Cross section after cutting the emitter window
SIC implantation is normally performed only for transistors that are to have a low breakdown-voltage. High-breakdown voltage transistors do not require this implant. Thus, fabricating both high and low breakdown devices in the same circuit requires five mask levels beyond the normal CMOS flow, although products requiring only one breakdown voltage can be fabricated with four mask levels beyond the standard CMOS flow.
A thin nitride spacer is then formed in the emitter window on the sidewall to prevent growth on the exposed extrinsic base poly during the following SiGe base growth. A timed 100:1 hydrofluoric acid (HF) dip etches away the remaining insulation oxide in the emitter window and creates a lateral gap between the base poly and silicon substrate (Figure 4)
FIGURE 4 Cross section after cavity created
The SiGe base is selectively grown in the emitter window and fills the lateral gap to form good contact to the extrinsic base poly (Figure 5).
FIGURE 5 Cross section after SiGe growth
The base consists of a 30-nm undoped Si 0.88 Ge0.12 layer together with a 30-nm boron-doped graded SiGe layer, where the Ge concentration is linearly ramped from about 12% down to 0%. Last, a 45-nm boron-doped Si layer is grown to cap the graded Ge region.. No growth on the nitride spacer is observable. The surface is very smooth and free of any particles and defects.
FIGURE 6 Final SiGe device cross section
The bipolar modules is completed by the lithography and etching of both the emitter and base polysilicon. After the SiGe module, the BiCMOS process merges back to the CMOS flow to complete the source and drain (S/D) implant and anneal, as well as back-end process up to seven layer of metalization. At the conclusion of the process, the SiGe bipolar is shown in the scanning electron microscope (SEM) micrograph in Figure7
FIGURE 7 SEM micrograph of device structure
Table 1 summarizes the performance of the SiGe NPN transistors made in this process technology.
TABLE 1
The performance of both the high breakdown (collector-emitter reakdown of 3.6V ) and high speed (collector-emitter breakdown of 2.5 V) bipolar devices are shown in Table 1.
The reduced breakdown voltage of the high-speed device is attributable to the changing implants that create a more heavily doped collector region, thereby increasing the multiplication factor at given reverse bias. As a trade-off, the device Fr increases from 58-78 GHz. As stated earlier, the process is designed so that multiple breakdown voltage devices are made available by the introduction of a mask that changes the collector implant doses. With multiple transistors, circuits that require large dynamic ranges or those that output significant power or interface to circuits outside the chip with 1 3-V swing will use the large breakdown voltage transistor. Those circuits requiring the highest speed performance, such as CML and low-level signal processing elements like receive-channel pre-amps and mixers, use the lower breakdown voltage device.
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